Low Frequency Oscillator with Ultra-low Short Circuit Current

ABSTRACT

In described examples, a sawtooth waveform generator generates a sawtooth waveform having a first rise time. A comb waveform circuit has a power terminal coupled to receive the sawtooth waveform from an output of the sawtooth waveform generator. The comb waveform circuit generates a comb waveform in response to the sawtooth waveform. The comb waveform has a second rise time that is faster than the first rise time.

TECHNICAL FIELD

This relates to low power oscillator circuits.

BACKGROUND

As the “internet of things” (IoT) becomes more widespread, smallportable or autonomous devices are being powered by micro-batteries orenergy harvesting systems. In such devices, minimal power consumption isimportant. In many such devices, an oscillator operating at a lowfrequency may be used. In many cases, the low frequency oscillator doesnot need to have good accuracy.

SUMMARY

In described examples, a sawtooth waveform generator generates asawtooth waveform having a first rise time. A comb waveform circuit hasa power terminal coupled to receive the sawtooth waveform from an outputof the sawtooth waveform generator. The comb waveform circuit generatesa comb waveform in response to the sawtooth waveform. The comb waveformhas a second rise time that is faster than the first rise time.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional kHz oscillator.

FIG. 2 is a set of waveforms that illustrate operation of the oscillatorof FIG. 1.

FIG. 3 is a block diagram of a kHz oscillator that includes a combwaveform generator to reduce short circuit current.

FIG. 4 is a set of waveforms that illustrate operation of the oscillatorof FIG. 3

FIG. 5 is a more detailed block diagram of the kHz oscillator of FIG. 3.

FIG. 6 is a schematic of a comb waveform generator that may be used inFIG. 3.

FIG. 7 is a schematic of another comb waveform generator that may beused in FIG. 3.

FIG. 8 is a schematic of another comb waveform generator that may beused in FIG. 3.

FIG. 9 is a set of voltage plots illustrating operation of the kHzoscillator of FIG. 8.

FIG. 10 is a schematic of a kHz oscillator that includes a duty cycledbias generator.

FIG. 11 is a set of plots illustrating operation of the duty cycled biasgenerator of FIG. 10.

FIG. 12 is a set of waveforms that illustrate operation of theoscillator of FIG. 10

FIG. 13 is a set of plots illustrating frequency of operation of the kHzoscillator of FIG. 10 over a range of parameters.

FIG. 14 is a set of plots illustrating power consumption of the kHzoscillator of FIG. 10 over a range of parameters.

FIG. 15 is a flow diagram illustrating operation of the kHz oscillatorsof FIGS. 3, 7, 8 and 10.

FIG. 16 is a block diagram of an example system that includes a lowpower oscillator.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

In the drawings, like elements are denoted by like reference numeralsfor consistency.

Small, low power devices are useful for a wide range of applications,such as: residential and industrial sensors, medical implants, smartcards, IoT nodes, and other applications. For such applications, a low“standby” or “quiescent current” (Iq) is desirable. To achieve an Iqthat is only a few nano-amperes (nA), a S/H technique (sample and hold)running on a very low frequency clock may provide good results. Forexample, an oscillator that generates a low frequency clock signal maybe operated in the sub 10 Khz range.

For many applications, an oscillator generating a low frequency clockdoes not need to have good accuracy, but needs to have very low currentconsumption, because the oscillator must operate continuously andtherefor contributes to Iq.

A relaxation oscillator is a conventional low frequency oscillatorarchitecture. A relaxation oscillator is a nonlinear electronicoscillator circuit that generates a non-sinusoidal repetitive outputsignal, such as a triangle wave or square wave. The circuit may includea feedback loop containing a device that repetitively charges acapacitor or inductor through a resistance until it reaches a thresholdlevel, and then discharges it again. Examples of such a device include:(a) a switching device, such as a transistor, comparator, relay oroperational amplifier; and (b) a negative resistance device, such as atunnel diode. The period of the oscillator depends on the time constantof the capacitor or inductor circuit. The switching device switchesabruptly between charging and discharging modes, and thus generates adiscontinuously changing repetitive waveform, which may be referred toas a sawtooth waveform.

The sawtooth signal has very slow signal transitions, which may resultin a large short-circuit current in a digital circuit of the feedbackloop that is tracking the sawtooth signal. Such short circuit currentmay limit ultra-low power operation in a sub 10 kHz oscillator.

Example embodiments include a comb waveform generator circuit to track asawtooth signal and generate a very fast voltage transition to therebyreduce short circuit current in a following digital buffer. As describedin more detail hereinbelow, this comb waveform generator circuit addszero extra current over a conventional circuit. Instead of directlyconnecting a sawtooth signal to the input of a CMOS (complementary metaloxide semiconductor) inverter/buffer, the sawtooth signal is convertedinto a fast edge comb waveform by passing the slow sawtooth waveformthrough a PMOS (p-type MOS) transistor. By connecting this fast edgewaveform to a CMOS inverter input, short-circuit current within the CMOSinverter is greatly reduced. Accordingly, extremely small short-circuitcurrent is achieved by faster edge rates at buffer/inverter inputs.

FIG. 1 is a block diagram of a conventional kHz oscillator. FIG. 2 is aset of waveforms that illustrate operation of the oscillator of FIG. 1.In this description, the term “kHz oscillator” refers to a low frequencyoscillator that operates in a range usually below 10 kHz, but someexamples may operate at frequencies above 10 kHz.

In this example, a sawtooth waveform is generated by capacitor 101,which is charged by current source 102 and discharged by switch element103. Switch element 103 is controlled by a dual edge one-shot circuit104. A CMOS inverter 105 receives the sawtooth signal v1 on signal line110, which is illustrated by plot 210 of FIG. 2, and generates an outputsignal v2 on signal line 111, which is illustrated by plot 211 of FIG.2. Flip-flop 106 toggles in response to each falling edge of sawtoothsignal v1 to generate a square wave signal Φ on signal line 112, whichis illustrated by plot 212 of FIG. 2. Square wave signal Φ may then beused to initiate each activation of switch device 103.

Assuming oscillator 100 is operating at approximately 1 kHz, the risingtransition time of each pulse of sawtooth signal v1 is approximately 0.5ms. This causes inverter 105 to switch slowly, as indicated by plot 211in FIG. 2. Such slow switching of a digital device may produce a “shortcircuit” current while both a pull-up and a pull-down transistor in theoutput stage of the device are turned on at the same time. Currentsource 102 may be the only component producing a continuous quiescentcurrent, which may be only a few nano-amps, but the short circuitcurrent may result in an average current consumption of 100 nA or morefor oscillator 100.

In another type of low frequency oscillator, a transistor leakage-basedtechnique may be used to reduce current consumption, but that techniqueis not stable for operation over a wide range of temperatures, such as−40 C to 125 C.

In another type of low frequency oscillator, a slow ramp signal (such asa sawtooth signal) is received as an input by a current biasedcomparator. This eliminates short-circuit current, but it requires extrabias current and a voltage reference for the comparator. Therefore, Iqusually exceeds 5 nA in such an oscillator.

FIG. 3 is a block diagram of a kHz oscillator 300 that includes a combwaveform generator 320 to reduce short circuit current in inverter 305and inverter 308. FIG. 4 is a set of waveforms that illustrate operationof the oscillator 300. A reduction in short-circuit current may beachieved by configuring inverter 305 to operate in a current-starvedmode. This may be done by supplying power to inverter 305 via a currentsource 321. In this manner, short circuit current may be limited to amaximum value that current source 321 can provide. This configurationmakes inverter 305 trip at a point near the NMOS transistor thresholdvoltage (nch Vt) of an NMOS transistor in the output stage of inverter305. NMOS transistor 1035 (FIG. 10) is an example. However, with onlythis improvement, the short circuit current produced in inverters 305and 308 may remain higher than desired.

As a further improvement, comb waveform generator 320 generates asharp-edged comb waveform v1 (which may be received as an input bybuffer/inverter 305) in response to the slow sawtooth waveform generatedby capacitor 301. As illustrated by plot 409 of FIG. 4, comb waveformgenerator 320 consumes zero extra current (beyond current that isconsumed to generate the sawtooth waveform on node 309).

In this example, a sawtooth waveform is generated on node 309 bycapacitor 301, which is charged by current source 302 and discharged byswitch element 303. Switch element 303 is controlled by a dual edgeone-shot circuit 304 (pulse waveform generator), which generates aperiodic pulse signal “D-mono” on signal line 313, as illustrated byplot 413 in FIG. 4. Switch element 303 may be a MOS transistor oranother type of switching device that can be controlled by one-shotcircuit 304. Comb waveform generator 320 receives sawtooth signal fromnode 309 and, in response thereto, generates a comb waveform v1 onsignal line 310. CMOS inverter 305: (a) receives the comb waveformsignal v1 on signal line 310, which is illustrated by plot 410 of FIG.4; and (b) generates an output signal v2 on signal line 311, which isillustrated by plot 411 of FIG. 4. Flip-flop 306 toggles in response toeach falling edge of sawtooth signal v1 to generate a square wave signalΦ on signal line 312, which is illustrated by plot 412 of FIG. 4. Squarewave signal Φ is then fed back to one-shot circuit 304 for triggeringeach activation of switch element 303.

As shown in FIG. 4, the rise time of signal v1 illustrated by plot 410is much faster than the rise time of the sawtooth signal “vsup”illustrated by plot 409. Therefore, inverter 305 of FIG. 3 switchesrapidly to generate output signal v2, and short circuit current issignificantly reduced (in comparison to a configuration in which asawtooth signal is received as an input by inverter 305). Similarly,because signal v2 has fast rise and fall times, inverter 308 of FIG. 3switches rapidly with insignificant short circuit current.

FIG. 3 shows two buffer stages, which are inverter 305 and inverter 308.In another example, these buffers may be implemented in differentconfigurations. For example, two non-inverting buffers may be used.Another example has only a single buffer stage.

In this example, inverter 305 is configured to operate in a currentstarved mode, using current source 321 to reduce short circuit current.In another example, current source 321 may be omitted, and inverter 305may be operated in a normal full power mode if short circuit current islow enough, due to fast switching provided by comb waveform generator320. For example, an average current of 2.7 nA may be drawn byoscillator 300 when inverter 305 is operated in current starved mode. Bycomparison, an average current of approximately 5 nA may be drawn in anexample when inverter 305 is operated in full power mode.

FIG. 5 is a more detailed block diagram of the kHz oscillator 300 ofFIG. 3. In this example, comb waveform generator 320 includes aninverter 530 that receives one-shot signal D-mono on signal line 313 atan input. The output of inverter 530 generates comb waveform v1 onsignal line 310. Inverter 530 receives its supply voltage (vsup) fromnode 309 in the form of a sawtooth waveform, as illustrated by plot 409of FIG. 4.

In this example, with a Vdd supply voltage of 1.4V and a chargingcurrent for capacitor 301 set at 1.2 nA by current source 302, totalaverage current for oscillator 300 is approximately 2.7 nA.

FIG. 6 is a schematic of comb waveform generator 320 that may be used inFIG. 3. In this example, comb waveform generator 320 includes a p-typeMOS (PMOS) transistor 631 and an n-type MOS (NMOS) transistor 632, whichare connected in series to implement inverter 530, as shown in FIG. 5. Asource terminal of PMOS transistor 631 is connected to signal line 309and receives the sawtooth waveform vsup. A drain terminal of PMOStransistor 631 is connected to a drain terminal of NMOS transistor 632.A source terminal of NMOS transistor 632 is coupled to supply bus Vss,which is usually connected to ground. A gate input for both MOStransistors 631, 632 is connected to receive the one-shot signal D-monoon signal line 313.

Referring again to FIG. 4, signal D-mono 413 stays low while sawtoothwaveform vsup 409 ramps up. This causes NMOS transistor 632 (FIG. 6) toremain off. As sawtooth waveform 409 continues to rise, PMOS transistor631 of FIG. 6 turns on and rapidly pulls up the output signal v1 onsignal line 310 (FIG. 6), as shown by pulse 414 in FIG. 4. This risingedge on signal line 310 (FIG. 6) flows through inverters 305 and 308(FIG. 6) and triggers flip-flop 306 to toggle, which triggers one-shotcircuit 304 (FIG. 6) to generate pulse 415 of FIG. 4. Pulse 415 turns onNMOS transistor 632 (FIG. 6) to pull signal v1 on signal line 310 low.Pulse 415 also turns on switch 303 (FIG. 6), which discharges capacitor301 (FIG. 6).

FIG. 7 is a schematic of another example comb waveform generator 720that may be used in FIG. 3. In this example, comb waveform generator 720includes a PMOS transistor 731 and an NMOS transistor 732, which areconnected in series to implement inverter 730. Inverter 730 is similarto inverter 530 of FIG. 5, except that a gate input for NMOS transistor732 is connected to receive the one-shot signal D-mono on signal line313, while a gate input for PMOS transistor 731 is connected to areference voltage “Vref”. In this example, the vsup on signal line 309must rise to a value that exceeds Vref before PMOS transistor 731 turnson to pull up signal v1 on output 710. In this manner, reference voltageVref sets a peak voltage height of comb waveform v1 on signal line 710.As Vref becomes higher, the peak of signal v1 becomes higher on signalline 710.

FIG. 8 is a schematic of another comb waveform generator 820 that may beused in FIG. 3. FIG. 9 is a set of voltage plots illustrating operationof kHz oscillator 800 of FIG. 8. This example uses a current sink 802 tocharge capacitor 801, such that sawtooth supply voltage vsup on signalline 809 ramps down as shown in plot 909 of FIG. 9. Switch device 803then discharges capacitor 801 in response to control signal “D-mono”generated on signal line 813 by one-shot circuit 804, in a similarmanner to operation of oscillator 300 of FIG. 3. Signal D-mono on signalline 813 is illustrated by plot 913 in FIG. 9. Signal Φ on signal line812 is illustrated by plot 912 in FIG. 9. In this example, negative combspikes are formed on signal line 810 as shown by plot 910 of FIG. 9.Positive comb spikes are formed on signal line 811 as shown by plot 911of FIG. 9.

In this example, comb waveform generator 820 includes a PMOS transistor831 and an NMOS transistor 832, which are connected in series toimplement inverter 830, for example. Inverter 830 may be similar toinverter 530 of FIG. 5, except that a gate input for PMOS transistor 831is connected to receive the one-shot signal D-mono on signal line 813,while a gate input for NMOS transistor 832 is connected to a referencevoltage “Vref”. While signal D-mono on signal line 813 is low, PMOStransistor 831 is turned on and pulls up output signal v1 on signal line810. This may cause a brief short circuit current through transistor832, but the duration of the D-mono pulse width is very small comparedto the clock period (i.e. 50 nS vs 500 us), so the impact is veryminimal to overall average Iq. In this example, vsup on signal line 809must fall below reference voltage Vref before NMOS transistor 832 turnson to pull down output 810. In this manner, reference voltage Vref setsa peak voltage height of comb waveform v1 on signal line 810. As Vrefbecomes lower, the peak of signal v1 becomes higher on signal line 810.

FIG. 10 is a schematic of a kHz oscillator 1000 that includes a dutycycled bias generator 1040. FIG. 11 is a set of plots illustratingoperation of the duty cycled bias generator of FIG. 10. FIG. 12 is a setof waveforms that illustrate operation of the oscillator of FIG. 10. Inthis example, oscillator 1000 is similar to oscillator 300 of FIG. 6,and it generates a square wave clock signal Φ on signal line 312, asillustrated by plot 1212 of FIG. 12.

Bias generator 1040 generates a bias voltage (vb) that is coupled to thegate of PMOS transistor 1002 to form a current source to providecharging current to capacitor 301. One-shot circuit 304 generates apulse on signal line 313 (as shown in plot 1213 of FIG. 12), whichcontrols switch element 303. A sawtooth waveform is thereby formed onsignal line 309, which provides power to comb waveform generatorinverter 530 (FIG. 5), as illustrated by plot 1209 of FIG. 12.

Initially, bias generator 1040 is reset by active low power on reset(porz) signal, as illustrated by plot 1150 in FIG. 11. The reset signalmay be used to control a number of switches (coupled to various nodeswithin bias generator 1040) to set or clear the nodes to initial states.After signal porz is deasserted (has a high logic level), bias generator1040 begins to operate. A current flow through transistor 1060, 1062 andresistor 1063 forms a voltage divider at node 1064. A bias voltage (vb)builds up across capacitor 1043, which is coupled to node 1064, asillustrated by plot 1151 of FIG. 11. A delayed “reference ready” signal(Iref_rdy) is asserted by charging a capacitor (not shown) to indicatethat the bias generator is operating and that bias signal vb is stable,as indicated by plot 1152 in FIG. 11.

A counter 1041 is coupled to receive clock signal Φ on signal line 312and configured to output a bias enable (bias_en) pulse on signal line1042 every N cycles of clock signal Φ. This example has a counter, butother examples may have different types of known or later developeddelay circuits to generate a periodic pulse. The bias enable signal maybe used to control several switches with bias generator 1040, such asswitch 1046 and 1047. Switches 1046, 1047 may be configured to beconductive only during the time a pulse is active on bias enable signalon signal line 1042. When the switches 1046, 1047 are in anon-conductive state, then current flow through transistors 1060, 1061and 1062 is blocked, and thereby power dissipation by bias generator1040 is minimized. During each time period in which no current isflowing through transistor 1060, 1062, 1062, capacitor 1043 maintainsthe bias voltage at an approximately steady value. Initially, counter1041 is disabled, and the bias enable signal on line 1042 remains activeuntil the reference ready signal is asserted.

Oscillator 1000 operates at a frequency that is determined by thecapacitance of capacitor C, the magnitude of current (I) that isprovided by current source 1002, and the threshold voltage of NMOStransistor 1035 (VtN1) that forms inverter 305, as shown by expression(1).

$\begin{matrix}{F = \frac{I}{C \times {VtN}\; 1}} & (1)\end{matrix}$

As described in more detail hereinabove, comb waveform generator 530generates a fast-rising pulse v1 on signal line 1010, as shown by plot1210 in FIG. 12. In this example, bias voltage vb is also coupled to thegate of PMOS transistor 1021 to form a current source that providespower to inverter 305, causing inverter 305 to operate in a currentstarved mode as described with regard to FIGS. 3-6. Negative pulsesignal v2 is generated by inverter 305 on signal line 1011 in responseto comb waveform v1, as illustrated by plot 1211 in FIG. 12.

Referring to FIG. 12, the period of clock signal Φ is approximately 1.0ms, with a frequency of approximately 1 kHz. FIG. 13 is a set of plotsillustrating frequency of operation of the kHz oscillator of FIG. 10over a range of parameters. Plot line 1371 represents nominal processparameters, while plot line 1372 represents strong process parameters,and plot line 1373 represents weak process parameters. In this example,at a nominal temperature of 30 C, the oscillator operates at 1 kHz.However, a fairly wide range of oscillator frequency may occur over arange of temperature and process parameters. As described hereinabove,some applications for low power systems may not be sensitive tovariations such as described herein.

FIG. 14 is a set of plots illustrating power consumption of the kHzoscillator of FIG. 10 over a range of parameters. Plot line 1471represents nominal process parameters, while plot line 1472 representsstrong process parameters, and plot line 1473 represents weak processparameters. In this example, at a nominal temperature of 30 C and at anoperating voltage of 1.4V, the oscillator dissipates approximately 3.8nW at an average current of 2.7 nA.

FIG. 15 is a flow diagram illustrating operation of the kHz oscillatorsof FIGS. 3, 7, 8 and 10. As further described hereinabove, theoscillators of FIGS. 3, 7 and 8 are relaxation oscillators in which acapacitive or inductive element is repetitively charged and dischargedunder control of a switching device. The period of the oscillatordepends on the time constant of the capacitor or inductor circuit. Theswitching device switches abruptly between charging and dischargingmodes, and thus generates a discontinuously changing repetitivewaveform, which may be referred to as a sawtooth waveform. At 1502, asawtooth waveform is generated by using a square wave generated by theoscillator that is fed back to control the switching device.

At 1504, a comb waveform generator converts the sawtooth waveform to acomb waveform that includes periodic pulses. The sawtooth waveform has arelatively slow rise time, but each pulse of the comb waveform has arelatively fast rise and fall time. A comb waveform generator may beimplemented using a two transistor inverter circuit that is powered bythe sawtooth waveform. A pulse signal may be received as an input by theinverter. When the pulse signal and the sawtooth waveform reach asufficient magnitude, an output of the inverter will rapidly transitionto form each pulse of the comb waveform. The pulse signal may be thesame signal that controls the switching device for the sawtooth waveformgenerator.

At 1506, a digital buffer converts the comb waveform to a digitalsignal. As described with regard to FIG. 3, a short circuit current maybe produced in the output stage of the digital buffer if the inputsignal has a slow transition. Therefore, short circuit current issignificantly reduced by providing the comb waveform to the digitalbuffer.

At 1508, a square wave is generated in response to the comb waveform. Asfurther described hereinabove, a flip-flop may be used to toggle betweentwo logic levels when clocked by the comb waveform. The resulting squarewaveform may then be used to control the switching device for thesawtooth waveform generator. For example, a one-shot timing circuit maybe triggered on each rise, or alternatively on each fall, of the squarewaveform. The one-shot circuit may be configured to generate a shortpulse each time it is triggered. The short pulse may be used to controlthe switching device and may be received as an input by the combwaveform generator buffer circuit.

System Example

FIG. 16 is a block diagram of an example system 1600 that includes a lowpower oscillator 1681 as described herein. Low frequency oscillator 1681may be similar to oscillator 1000 of FIG. 10, for example. Oscillator1681 may be coupled to processing logic 1682 to provide a clock signalfor use by processing logic 1682. Processing logic 1682 may be any knownor later developed processing logic that requires a low frequency clocksignal for operation. Similarly, oscillator 1681 may be coupled tosensing logic 1683 for use by sensing logic 1683. Sensing logic 1683 maybe any of a variety of known or later developed circuits or interfacesthat may be used to sense external conditions, parameters, signals, etc.Processing logic 1682 may be coupled to sensing logic 1683 and controlthe operation of sensing logic 1683. Also, system 1600 may includeadditional interface logic and storage circuitry.

Energy storage 1680 provides energy to oscillator 1681 and to the othercircuitry within system 1600. Energy storage 1680 device may be abattery in some examples. In other examples, energy storage 1680 may bea capacitor or inductor that is charged by energy scavenging from thesurrounding environment, such as by near field coupling, light energy,thermal energy, vibration energy, etc. Low power operation of oscillator1681 conserves power available for energy storage 1680.

System 1600 may be fabricated on an integrated circuit (IC) die usingknown or later developed fabrication techniques and may be packaged asan IC package using known or later developed packaging techniques.

Other Examples

In described examples, a low power oscillator operates with a frequencyof approximately 1 kHz. In other examples, the operating frequency maybe higher or lower. For example, another low power oscillator mayoperate at a frequency of approximately 10 kHz.

Various configurations of inverting buffers are described herein. Inother examples, non-inverting buffers may be used.

In described examples, a flip-flop logic module generates the squarewave signal. In another example, an alternative type of state machinemay be used to generate a square wave.

In another example, a square wave with other than a 50/50 on/off cyclemay be implemented.

In described examples, a comb waveform generator is coupled to arelaxation oscillator. In another example, a comb waveform generator (asdescribed herein) may be coupled another type of digital circuit, whichmay benefit from fast rise time signals to reduce short circuit currentwithin digital logic.

In this description, the term “couple” and derivatives thereof mean anindirect, direct, optical, and/or wireless electrical connection. Thus,if a first device couples to a second device, that connection may bethrough a direct electrical connection, through an indirect electricalconnection via other devices and connections, through an opticalelectrical connection, and/or through a wireless electrical connection.

Modifications are possible in the described examples, and other examplesare possible, within the scope of the claims.

What is claimed is:
 1. An integrated circuit (IC) comprising: a sawtoothwaveform generator to generate a sawtooth waveform having a first risetime; and a comb waveform circuit, having a power terminal coupled toreceive the sawtooth waveform from an output of the sawtooth waveformgenerator, to generate a comb waveform in response to the sawtoothwaveform, the comb waveform having a second rise time that is fasterthan the first rise time.
 2. The IC of claim
 1. further comprising apulse waveform generator to generate a periodic pulse waveform, whereinthe sawtooth waveform generator and the comb waveform circuit haverespective inputs coupled to receive the periodic pulse waveform from anoutput of the pulse waveform generator.
 3. The IC of claim 1, whereinthe comb waveform circuit includes: a p-type metal oxide semiconductor(PMOS) transistor having a drain terminal, a source terminal and a gateterminal, the source terminal being connected to the output of thesawtooth waveform generator; and an n-type metal oxide semiconductor(NMOS) transistor having a drain terminal, a source terminal and a gateterminal, the source terminal of the NMOS transistor being connected toa supply bus, and the drain terminal of the NMOS transistor beingconnected to the drain terminal of the PMOS transistor at a node thatforms an output of the comb waveform circuit.
 4. The IC of claim 3.further comprising a pulse waveform generator to generate a periodicpulse waveform, wherein the sawtooth waveform generator and the combwaveform circuit have respective inputs coupled to receive the periodicpulse waveform from an output of the pulse waveform generator, and thegate terminal of the PMOS transistor and the gate terminal of the NMOStransistor are coupled to receive the periodic pulse waveform from theoutput of the pulse waveform generator.
 5. The IC of claim 3, furthercomprising a pulse waveform generator to generate a periodic pulsewaveform, wherein: the sawtooth waveform generator is configured togenerate a sawtooth waveform having a rising ramp; and the gate terminalof the NMOS transistor is connected to an output of the pulse waveformgenerator, and the gate terminal of the PMOS transistor is connected toa reference voltage signal line.
 6. The IC of claim 3, furthercomprising a pulse waveform generator to generate a periodic pulsewaveform, wherein: the sawtooth waveform generator is configured togenerate a sawtooth waveform having a falling ramp; and the gateterminal of the NMOS transistor is connected to an output of the pulsewaveform generator, and the gate terminal of the PMOS transistor isconnected to a reference voltage signal line.
 7. The IC of claim 1,wherein an oscillator circuit includes the sawtooth waveform generatorand the comb waveform circuit, and the IC further comprises: a bufferhaving an input coupled to an output of the comb waveform circuit; aflip-flop having a clock input and an output, the clock input beingcoupled to an output of the buffer, and the flip-flop being configuredto toggle the flip-flop output in response to the clock input; andfeedback logic coupled between the flip-flop output and the sawtoothwaveform generator.
 8. The IC of claim 7, wherein the buffer includesone or more serially connected inverters, and at least one of theserially connected inverters has a power terminal connected to a currentsource.
 9. An oscillator circuit comprising: a sawtooth waveformgenerator to generate a sawtooth voltage signal having a rise time; acomb waveform generator having a power terminal coupled to receive thesawtooth voltage signal from an output of the sawtooth waveformgenerator; and a buffer having an input coupled to an output of the combwaveform generator.
 10. The oscillator circuit of claim 9, furthercomprising: a flip-flop having a clock input and an output, the clockinput being coupled to an output of the buffer, and the flip-flop beingconfigured to toggle the flip-flop output in response to the clockinput; and feedback logic coupled between the flip-flop output and thesawtooth waveform generator.
 11. The oscillator circuit of claim 9,wherein the comb waveform generator includes an inverter having thepower terminal, an input and an output, and the input of the inverter iscoupled to receive a periodic pulse signal.
 12. The oscillator circuitof claim 11, wherein the inverter includes: a p-type metal oxidesemiconductor (PMOS) transistor having a drain terminal, a sourceterminal and a gate terminal, the source terminal being connected to theoutput of the sawtooth waveform generator; and an n-type metal oxidesemiconductor (NMOS) transistor having a drain terminal, a sourceterminal and a gate terminal, the source terminal of the NMOS transistorbeing connected to a supply bus, and the drain terminal of the NMOStransistor being connected to the drain terminal of the PMOS transistorat a node that forms the output of the inverter.
 13. The oscillatorcircuit of claim 12, further comprising a pulse waveform generator togenerate a periodic pulse waveform, wherein the sawtooth waveformgenerator and the comb waveform circuit have respective inputs coupledto receive the periodic pulse waveform from an output of the pulsewaveform generator, and the gate terminal of the PMOS transistor and thegate terminal of the NMOS transistor are coupled to receive the periodicpulse waveform from the output of the pulse waveform generator.
 14. Theoscillator circuit of claim 12, further comprising a pulse waveformgenerator to generate a periodic pulse waveform, wherein: the sawtoothwaveform generator is configured to generate a sawtooth waveform havinga rising ramp; and the gate terminal of the NMOS transistor is connectedto an output of the pulse waveform generator, and the gate terminal ofthe PMOS transistor is connected to a reference voltage signal line. 15.The oscillator circuit of claim 12, further comprising a pulse waveformgenerator to generate a periodic pulse waveform, wherein: the sawtoothwaveform generator is configured to generate a sawtooth waveform havinga falling ramp; and the gate terminal of the NMOS transistor isconnected to an output of the pulse waveform generator, and the gateterminal of the PMOS transistor is connected to a reference voltagesignal line.
 16. The oscillator circuit of claim 9, wherein the bufferincludes one or more serially connected inverters.
 17. The oscillatorcircuit of claim 16, wherein at least one of the serially connectedinverters has a power terminal connected to a current source.
 18. Amethod of operating a circuit, the method comprising: generating asawtooth waveform having a first rise time in response to a periodicsignal; and converting the sawtooth waveform to a comb waveform having asecond rise time that is faster than the first rise time, by using thesawtooth waveform to power a buffer circuit using current from only thesawtooth waveform.
 19. The method of claim 18, wherein converting thesawtooth waveform to the comb waveform includes receiving the sawtoothwaveform at a source terminal of a transistor of the buffer circuit,receiving a reference voltage at a gate terminal of the transistor, andgenerating the comb waveform at a drain terminal of the transistor. 20.The method of claim 19, wherein the transistor is a first transistor,and the method further comprises receiving a pulse signal at a gateterminal of a second transistor of the buffer circuit, wherein a drainterminal of the second transistor is connected to the drain terminal ofthe first transistor, and a source terminal of the second transistor isconnected to a supply bus.